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data sheet mos integrated circuit m pd78p4038y the m pd78p4038y, 78k/iv series' product, is a one-time prom or eprom version of the m pd784035y, m pd784036y, m pd784037y, and m pd784038y with internal masked rom. since user programs can be written to prom, this microcontroller is best suited for evaluation in system development, manufacture of small quantities of multiple products, and fast start-up of applications. for specific functions and other detailed information, consult the following user's manual. this manual is required reading for design work. m pd784038, 784038y sub-series user's manual, hardware : u11316e 78k/iv series user's manual, instruction : u10905e features ? compatible with the m pd78p238, m pd78p4026, and m pd78p4038 ? internal prom: 128 kbytes ? m pd78p4038ykk-t : eprom (best suited for system evaluation) ? m pd78p4038ygc-3b9 : prom (best suited for manufacture of small quantities) m pd78p4038ygc-8bt : prom (best suited for manufacture of small quantities) m pd78p4038ygk-be9 : prom (best suited for manufacture of small quantities) ? internal ram: 4,352 bytes ? supply voltage: v dd = 2.7 to 5.5 v ? qtop tm microcomputer remark the qtop microcomputer is a microcomputer with a built-in one-time prom that is totally supported by nec. the support includes writing application programs, marking, screening, and verification. ordering information part number package internal rom m pd78p4038ygc-3b9 80-pin plastic qfp (14 14 2.7 mm) one-time prom m pd78p4038ygc-8bt 80-pin plastic qfp (14 14 1.4 mm) one-time prom m pd78p4038ygc- -3b9 80-pin plastic qfp (14 14 mm) one-time prom (qtop microcomputer) m pd78p4038ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) one-time prom m pd78p4038ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) one-time prom (qtop microcomputer) m pd78p4038ykk-t 80-pin ceramic wqfn (14 14 mm) eprom in this reference, all rom components that are common to one-time prom and eprom are referred to as prom. the mark shows major revised points. the information in this document is subject to change without notice. 16/8-bit single-chip microcontroller document no. u10742ej2v0ds00 (2nd edition) date published july 1998 j cp(k) printed in japan 1995
m pd78p4038y 2 quality grade part number package quality grade m pd78p4038ygc-3b9 80-pin plastic qfp (14 14 2.7 mm) standard (for general electronic equipment) m pd78p4038ygc-8bt 80-pin plastic qfp (14 14 1.4 mm) standard (for general electronic equipment) m pd78p4038ygc- -3b9 80-pin plastic qfp (14 14 1.4 mm) standard (for general electronic equipment) m pd78p4038ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard (for general electronic equipment) m pd78p4038ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard (for general electronic equipment) m pd78p4038ykk-t 80-pin ceramic wqfn (14 14 mm) not applied (for function evaluation) please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. caution the eprom versions of the m pd78p4038y are not intended for use in mass-produced products; they do not have reliability high enough for such purposes. their use should be restricted to functional evaluation in experiment or trial manufacture. remark is rom code suffix.
m pd78p4038y 3 78k/iv series product development diagram : product under mass production : product under preparation standard products development assp development pd784026 a/d converters, 16-bit timers, and power management functions have been enhanced. internal memory has been expanded. pin-compatible with the pd784026 pd784038y pd784038 connectable to the i 2 c bus 100 pins i/o has been enhanced. internal memory has been expanded. pd784216y pd784216 connectable to the multimaster i 2 c bus pd784054 built-in 10-bit a/d converter pd784046 80 pins rom correction function has been added. pd784225y pd784225 connectable to the multimaster i 2 c bus internal memory has been expanded. rom correction function has been added. pd784218y pd784218 connectable to the multimaster i 2 c bus m m m m m m m m m m m m pd784908 built-in iebus tm controller functions of the pd784915 have been enhanced. pd784928y pd784928 connectable to the multimaster i 2 c bus pd784955 dc inverter control pd784915 software servo control built-in analog circuit for vcr timers have been enhanced. m functions of the pd784908 have been enhanced. internal memory has been expanded. rom correction function has been added. pd784937 m m m m m m m
m pd78p4038y 4 functions (1/2) note additional function pins are included in the i/o pins. item number of basic instructions (mnemonics) general-purpose register minimum instruction execution time internal memory memory space i/o ports additional function pins note real-time output ports timer/counter pwm outputs serial interface a/d converter d/a converter functions 113 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) 125 ns/250 ns/500 ns/1,000 ns (at 32 mhz) 128 kbytes (can be changed to 48 k, 64 k, or 96 kbytes by software) 4,352 bytes (can be changed to 2,048 or 3,584 bytes by software) program and data: 1 mbyte 64 8 56 54 24 8 4 bits 2, or 8 bits 1 timer/counter 0: timer register 1 pulse output capability capture register 1 toggle output compare register 2 pwm/ppg output one-shot pulse output timer/counter 1: timer register 1 pulse output capability capture register 1 real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability capture register 1 toggle output capture/compare register 1 pwm/ppg output compare register 1 timer 3 : timer register 1 compare register 1 12-bit resolution 2 channels uart/ioe (3-wire serial i/o): 2 channels (incorporating baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus): 1 channel 8-bit resolution 8 channels 8-bit resolution 2 channels prom ram total input input/output pins with pull- up resistor led direct drive outputs transistor direct drive
m pd78p4038y 5 item clock output watchdog timer standby interrupt supply voltage package (2/2) functions selected from f clk , f clk /2, f clk /4, f clk /8, or f clk /16 (can be used as a 1-bit output port) 1 channel halt/stop/idle mode 24 (17 internal, 7 external (sampling clock variable input: 1)) brk instruction, brkcs instruction, operand error 1 internal, 1 external 16 internal, 6 external 4-level programmable priority 3 operation statuses: vectored interrupt, macro service, context switching v dd = 2.7 to 5.5 v 80-pin plastic qfp (14 14 2.7 mm) 80-pin plastic qfp (14 14 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm) 80-pin ceramic wqfn (14 14 mm) hardware source software source nonmaskable maskable
m pd78p4038y 6 contents 1. differences between m pd78p4038y and masked rom products .................... 7 2. pin configuration (top view) ......................................................................................... 8 3. block diagram ..................................................................................................................... 11 4. list of pin functions ......................................................................................................... 12 4.1 pins for normal operating mode ................................................................................................. 12 4.2 pins for prom programming mode (v pp +5 v or +12.5 v, reset = l) .............................. 15 4.2.1 pin functions .................................................................................................................. 15 4.2.2 pin functions .................................................................................................................. 16 4.3 i/o circuits for pins and handling of unused pins .................................................................. 17 5. internal memory switching (ims) register ............................................................ 20 6. prom programming ............................................................................................................ 21 6.1 operation mode .............................................................................................................................. 2 1 6.2 prom write sequence .................................................................................................................. 23 6.3 prom read sequence .................................................................................................................. 27 7. erasure characteristics ( m pd78p4038ykk-t only) ............................................... 28 8. protective film covering the erasure window ( m pd78p4038ykk-t only) .. 28 9. quality ............................................................................................................................... ...... 28 10. screening one-time prom products .......................................................................... 28 11. electrical characteristics ......................................................................................... 29 12. package drawings ............................................................................................................. 55 13. recommended soldering conditions ........................................................................ 59 appendix a development tools .......................................................................................... 61 appendix b conversion socket (ev-9200gc-80) and conversion adapter (tgk-080sdw) .......................................................................................................... 64 appendix c related documents .......................................................................................... 67
m pd78p4038y 7 1. differences between m pd78p4038y and masked rom products the m pd78p4038y is produced by replacing the masked rom in the m pd784035y, m pd784036y, m pd784037y, or m pd784038y with prom to which data can be written. the functions of the m pd78p4038y are the same as those of the m pd784035y, m pd784036y, m pd784037y, or m pd784038y except for the prom specification such as writing and verification, except that the prom size can be changed to 48 k, 64 k, or 96 kbytes, and except that the internal ram size can be changed to 2,048 or 3,584 bytes. table 1-1 shows the differences between these products. table 1-1. differences between the m pd78p4038y and masked rom products product name item internal program memory internal ram package m pd78p4038y 128-kbyte prom can be changed to 48 k, 64 k, or 96 kbytes by ims 4,352-byte internal ram can be changed to 2,048 or 3,584 bytes by ims m pd784038y 128-kbyte masked rom 4,352-byte internal ram m pd784037y 96-kbyte masked rom 3,584-byte internal ram m pd784036y 64-kbyte masked rom m pd784035y 48-kbyte masked rom 2,048-byte internal ram 80-pin plastic qfp (14 14 2.7 mm) 80-pin plastic qfp (14 14 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm) 80-pin ceramic wqfn (14 14 mm)
m pd78p4038y 8 2. pin configuration (top view) (1) normal operating mode ? 80-pin plastic qfp (14 14 2.7 mm) m pd78p4038ygc-3b9, m pd78p4038ygc- -3b9 ? 80-pin plastic qfp (14 14 1.4 mm) m pd78p4038ygc-8bt ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78p4038ygk-be9, m pd78p4038ygk- -be9 ? 80-pin ceramic wqfn (14 14 mm) m pd78p4038ykk-t note connect the test pin to v ss0 directly. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd0 p17 p16 p15 p14/t x d2/so2 p13/r x d2/si2 p12/asck2/sck2 p11/pwm1 p10/pwm0 test note v ss0 astb/clkout p40/ad0 p41/ad1 p42/ad2 p32/sck0/scl p33/so0/sda p34/ to0 p35/ to1 p36/ to2 p37/ to3 reset v dd1 x2 x1 v ss1 p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p66/ wait/hldrq p65/ wr p64/rd p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p31/ txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi av ref3 av ref2 ano1 ano0 av ss av ref1 av dd p77/ani7 p76/ani6 p75/ani5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
m pd78p4038y 9 p60-p67 : port 6 p70-p77 : port 7 pwm0, pwm1 : pulse width modulation output rd : read strobe refrq : refresh request reset : reset rxd, rxd2 : receive data sck0-sck2 : serial clock scl : serial clock sda : serial data si0-si2 : serial input so0-so2 : serial output test : test to0-to3 : timer output txd, txd2 : transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait : wait wr : write strobe x1, x2 : crystal a8-a19 : address bus ad0-ad7 : address/data bus ani0-ani7 : analog input ano0, ano1 : analog output asck, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref1 -av ref3 : reference voltage av ss : analog ground ci : clock input clkout : clock output hldak : hold acknowledge hldrq : hold request intp0-intp5 : interrupt from peripherals nmi : non-maskable interrupt p00-p07 : port 0 p10-p17 : port 1 p20-p27 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5
m pd78p4038y 10 (2) prom programming mode ? 80-pin plastic qfp (14 14 2.7 mm) m pd78p4038ygc-3b9, m pd78p4038ygc- -3b9 ? 80-pin plastic qfp (14 14 1.4 mm) m pd78p4038ygc-8bt ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78p4038ygk-be9, m pd78p4038ygk- -be9 ? 80-pin ceramic wqfn (14 14 mm) m pd78p4038ykk-t caution l : connect these pins separately to the v ss pins through 10-k w pull-down resistors. v ss : to be connected to the ground. open : nothing should be connected on these pins. reset: set a low-level input. a0-a16 : address bus reset : reset ce : chip enable v dd : power supply d0-d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v pp v ss open a0 a1 a2 reset v dd open (l) v ss d0 d1 d2 d3 d4 d5 d6 d7 (l) pgm ce oe v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a15 a14 a13 a12 a11 a10 a16 a8 a7 a6 a5 a4 a3 v dd (l) (l) v ss open open open v ss v ss a9 open open (l) open
m pd78p4038y 11 3. block diagram note in the prom programming mode. nmi intp0-intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00-p03 p04-p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0-ani7 av dd av ref1 av ss intp5 a/d converter d/a converter real-time output port pwm uart/ioe2 r x d/si1 t x d/so1 asck/sck1 r x d2/si2 t x d2/so2 asck2/sck2 sck0/scl so0/sda si0 astb/clkout ad0-ad7 a8-a15 a16-a19 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 p70-p77 reset test x1 x2 v pp note v dd0 , v dd1 v ss0 , v ss1 rd wr wait/hldrq refrq/hldak d0-d7 note a0-a16 note ce note oe note pgm note p00-p07 p10-p17 baud-rate generator clock output uart/ioe1 bus interface port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 system control watchdog timer baud-rate generator clocked serial interface timer 3 (16 bits) prom (128 kbytes) ram (3,840 bytes) 78 k/iv cpu core (ram 512 bytes) timer/counter 2 (16 bits) timer/counter 1 (16 bits) timer/counter 0 (16 bits) programmable interrupt controller
m pd78p4038y 12 pin p00-p07 p10 p11 p12 p13 p14 p15-p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34-p37 p40-p47 i/o i/o i/o input i/o i/o alternate-function C pwm0 pwm1 asck2/sck2 r x d2/si2 t x d2/so2 C nmi intp0 intp1 intp2/ci intp3 intp4/asck/sck1 intp5 si0 r x d/si1 t x d/so1 sck0/scl so0/sda to0-to3 ad0-ad7 function port 0 (p0): 8-bit i/o port. functions as a real-time output port (4 bits 2). inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive a transistor. port 1 (p1): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive led. port 2 (p2): 8-bit input-only port. p20 does not function as a general-purpose port (nonmaskable interrupt). however, the input level can be checked by an interrupt service routine. the use of the pull-up resistors can be specified by software for pins p22 to p27 (in units of 6 bits). the p25/intp4/asck/sck1 pin functions as the sck1 output pin by csim1. port 3 (p3): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. port 4 (p4): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive led. 4. list of pin functions 4.1 pins for normal operating mode (1) port pins (1/2)
m pd78p4038y 13 (1) port pins (2/2) pin p50-p57 p60-p63 p64 p65 p66 p67 p70-p77 i/o i/o i/o i/o function port 5 (p5): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive led. port 6 (p6): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. port 7 (p7): 8-bit i/o port. inputs and outputs can be specified bit by bit. alternate-function a8-a15 a16-a19 rd wr wait/hldrq refrq/hldak ani0-ani7
m pd78p4038y 14 (2) non-port pins (1/2) pin to0-to3 ci r x d r x d2 t x d t x d2 asck asck2 sda si0 si1 si2 so0 so1 so2 sck0 sck1 sck2 scl nmi intp0 intp1 intp2 intp3 intp4 intp5 ad0-ad7 a8-a15 a16-a19 rd wr wait refrq hldrq hldak astb clkout i/o output input input output input i/o input output i/o input i/o output output output output input output input output output output function timer output input of a count clock for timer/counter 2 serial data input (uart0) serial data input (uart2) serial data output (uart0) serial data output (uart2) baud rate clock input (uart0) baud rate clock input (uart2) serial data i/o (2-wire serial i/o, i 2 c bus) serial data input (3-wire serial i/o0) serial data input (3-wire serial i/o1) serial data input (3-wire serial i/o2) serial data output (3-wire serial i/o0) serial data output (3-wire serial i/o1) serial data output (3-wire serial i/o2) serial clock i/o (3-wire serial i/o0) serial clock i/o (3-wire serial i/o1) serial clock i/o (3-wire serial i/o2) serial clock i/o (2-wire serial i/o, i 2 c bus) external interrupt request C input of a count clock for timer/counter 1 capture/trigger signal for cr11 or cr12 input of a count clock for timer/counter 2 capture/trigger signal for cr22 input of a count clock for timer/counter 2 capture/trigger signal for cr21 input of a count clock for timer/counter 0 capture/trigger signal for cr02 C input of a conversion start trigger for a/d converter time multiplexing address/data bus (for connecting external memory) high-order address bus (for connecting external memory) high-order address bus during address expansion (for connecting external memory) strobe signal output for reading the contents of external memory strobe signal output for writing on external memory wait signal insertion refresh pulse output to external pseudo static memory input of bus hold request output of bus hold response latch timing output of time multiplexing address (a0-a7) (for connecting external memory) clock output alternate-function p34-p37 p23/intp2 p30/si1 p13/si2 p31/so1 p14/so2 p25/intp4/sck1 p12/sck2 p33/so0 p27 p30/r x d p13/r x d2 p33/sda p31/t x d p14/t x d2 p32/scl p25/intp4/asck p12/asck2 p32/sck0 p20 p21 p22 p23/ci p24 p25/asck/sck1 p26 p40-p47 p50-p57 p60-p63 p64 p65 p66/hldrq p67/hldak p66/wait p67/refrq clkout astb
m pd78p4038y 15 (2) non-port pins (2/2) pin reset x1 x2 ani0-ani7 ano0, ano1 av ref1 av ref2 , av ref3 av dd av ss v dd0 note 1 v dd1 note 1 v ss0 note 2 v ss1 note 2 test i/o input input C input output C function chip reset crystal input for system clock oscillation (a clock pulse can also be input to the x1 pin.) analog voltage inputs for the a/d converter analog voltage inputs for the d/a converter application of a/d converter reference voltage application of d/a converter reference voltage positive power supply for the a/d converter ground for the a/d converter positive power supply of the port part positive power supply except for the port part ground of the port part ground except for the port part directly connect to v ss0 . (the test pin is for the ic test.) alternate-function C C p70-p77 C C pin name v pp reset a0-a16 d0-d7 ce oe pgm v dd v ss i/o C input i/o input C C function prom programming mode selection high voltage input during program write or verification prom programming mode selection address bus data bus prom enable input/program pulse input read strobe input to prom program/program inhibit input during prom programming mode positive power supply gnd notes 1. the potential of the v dd0 pin must be equal to that of the v dd1 pin. 2. the potential of the v ss0 pin must be equal to that of the v ss1 pin. 4.2 pins for prom programming mode (v pp +5 v or +12.5 v, reset = l) 4.2.1 pin functions
m pd78p4038y 16 4.2.2 pin functions (1) v pp (programming power supply): input input pin for setting the m pd78p4038y to the prom programming mode. when the input voltage on this pin is +5 v or more and when reset input goes low, the m pd78p4038y enters the prom programming mode. when ce is made low for v pp = +12.5 v and oe = high, program data on d0 to d7 can be written into the internal prom cell selected by a0 to a16. (2) reset (reset): input input pin for setting the m pd78p4038y to the prom programming mode. when input on this pin is low, and when the input voltage on the v pp pin goes +5 v or more, the m pd78p4038y enters the prom programming mode. (3) a0 to a16 (address bus): input address bus that selects an internal prom address (0000h to 1ffffh) (4) d0 to d7 (data bus): i/o data bus through which a program is written on or read from internal prom (5) ce (chip enable): input this pin inputs the enable signal from internal prom. when this signal is active, a program can be written or read. (6) oe (output enable): input this pin inputs the read strobe signal to internal prom. when this signal is made active for ce = low, a one- byte program in the internal prom cell selected by a0 to a16 can be read onto d0 to d7. (7) pgm (program): input the input pin for the operation mode control signal of the internal prom. upon activation, writing to the internal prom is enabled. upon inactivation, reading from the internal prom is enabled. (8) v dd positive power supply pin (9) v ss ground potential pin
m pd78p4038y 17 4.3 i/o circuits for pins and handling of unused pins table 4-1 describes the types of i/o circuits for pins and the handling of unused pins. figure 4-1 shows the configuration of these various types of i/o circuits. table 4-1. types of i/o circuits for pins and handling of unused pins (1/2) pin p00-p07 p10/pwm0 p11/pwm1 p12/asck2/sck2 p13/r x d2/si2 p14/t x d2/so2 p15-p17 p20/nmi p21/intp0 p22/intp1 p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 p26/intp5 p27/si0 p30/r x d/si1 p31/t x d/so1 p32/sck0/scl p33/so0/sda p34/to0-p37/to3 p40/ad0-p47/ad7 p50/a8-p57/a15 p60/a16-p63/a19 p64/rd p65/wr p66/wait/hldrq p67/refrq/hldak p70/ani0-p77/ani7 ano0, ano1 astb/clkout recommended connection method for unused pins input state: to be connected to v dd0 output state: to be left open to be connected to v dd0 or v ss0 to be connected to v dd0 input state: to be connected to v dd0 output state: to be left open to be connected to v dd0 input state: to be connected to v dd0 output state: to be left open input state: to be connected to v dd0 or v ss0 output state: to be left open to be left open i/o circuit type 5-h 8-c 5-h 2 2-c 8-c 2-c 5-h 10-b 5-h 20-a 12 4-b i/o i/o input i/o input i/o i/o output
m pd78p4038y 18 table 4-1. types of i/o circuits for pins and handling of unused pins (2/2) caution when the i/o mode of an i/o alternate-function pin is unpredictable, connect the pin to v dd0 through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when i/o is switched by software). remark since type numbers are consistent in the 78k series, those numbers are not always serial in each product. (some circuits are not included.) recommended connection method for unused pins C to be connected to v ss0 directly to be connected to v ss0 to be connected to v dd0 i/o input pin reset test av ref1 -av ref3 av ss av dd i/o circuit type 2 1-a C
m pd78p4038y 19 figure 4-1. i/o circuits for pins type 1-a type 2-c type 2 type 4-b type 8-c type 10-b type 5-h type 12 type 20-a in v dd0 v ss0 p n in schmitt trigger input with hysteresis characteristics schmitt trigger input with hysteresis characteristics in v dd0 p pull-up enable data v dd0 v ss0 p n out output disable push-pull output which can output high impedance (both the positive and negative channels are off.) data v dd0 v ss0 p n in/out output disable v dd0 p pull-up enable input enable data v dd0 v ss0 p n in/out output disable v dd0 p pull-up enable n p analog output voltage out data v dd0 v ss0 p n in/out output disable v dd0 p pull-up enable open drain data comparator v dd0 v ss0 av ref av ss p (threshold voltage) p n n in/out output disable input enable +
m pd78p4038y 20 5. internal memory switching (ims) register this register enables the software to avoid using part of the internal memory. the ims register can be set to establish the same memory mapping as used in rom products that have different internal memory (rom and ram) configurations. the ims register is set using 8-bit memory operation instructions. a reset input sets the ims register to ffh. figure 5-1. internal memory switching (ims) register the ims is not contained in a mask rom product ( m pd784035y, m pd784036y, m pd784037y, or m pd784038y). but the action is not affected if the write command to the ims is executed to the mask rom product. ims ims7 ims6 ims5 ims4 ims3 ims2 ims1 ims0 76543210 0fffch address ffh after reset w r/w ims0-7 ffh eeh dch same as the pd784038y memory size cch m same as the pd784037y m same as the pd784036y m same as the pd784035y m
m pd78p4038y 21 6. prom programming the m pd78p4038y has an on-chip 128-kb prom device for use as program memory. when programming, set the v pp and reset pins for prom programming mode. see (2) in chapter 2 with regard to handling of other, unused pins. 6.1 operation mode prom programming mode is selected when +5 v or +12.5 v is added to the v pp pin or low-level input is added to the reset pin. this mode can be set to operation mode by setting the ce pin, oe pin, and pgm pin as shown in table 6-1 below. in addition, the prom contents can be read by setting read mode. table 6-1. prom programming operation mode pin reset v pp v dd ce oe pgm d0-d7 operation mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high impedance byte write l h l data input program verify l l h data output program inhibit h h high impedance ll read +5 v +5 v l l h data output output disable l h high impedance standby h high impedance remark = l or h
m pd78p4038y 22 (1) read mode set ce to l and oe to l to set read mode. (2) output disable mode set oe to h to set high impedance for data output and output disable mode. consequently, if several m pd78p4038y devices are connected to a data bus, the oe pins can be controlled to select data output from any of the devices. (3) standby mode set ce to h to set standby mode. in this mode, data output is set to high impedance regardless of the oe setting. (4) page data latch mode at the beginning of page write mode, set ce to h, pgm to h, and oe to l to set page data latch mode. in this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit. (5) page write mode after latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program pulse (active, low) to the pgm pin with both ce and oe set to h causes page write to be executed. later, setting both ce and oe to l causes program verification to be executed. if programming is not completed after one program pulse, the write and verify operations may be repeated x times (where x 10). (6) byte write mode adding a 0.1 ms program pulse (active, low) to the pgm pin with both ce and oe set to h causes byte write to be executed. later, setting oe to l causes program verification to be executed. if programming is not completed after one program pulse, the write and verify operations may be repeated x times (where x 10). (7) program verify mode set ce to l, pgm to h, and oe to l to set program verify mode. use verify mode for verification following each write operation. (8) program inhibit mode program inhibit mode is used to write to a single device when several m pd78p4038y devices are connected in parallel to oe , v pp , and d0 to d7 pins. use the page write mode or byte write mode described above for each write operation. write operations cannot be done for devices in which the pgm pin has been set to h.
m pd78p4038y 23 6.2 prom write sequence figure 6-1. page program mode flowchart remark g = start address n = program end address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 0.1 ms program pulse x = x + 1 latch no x = 10 ? yes verify 4 bytes pass address = n ? yes v dd = 4.5-5.5 v, v pp = v dd verify all bytes pass no all pass write end fail defective address = address + 1 fail
m pd78p4038y 24 figure 6-2. page program mode timing page data latch page program program verify data input data output a2-a16 a0, a1 d0-d7 v pp v dd v pp v dd +1.5 v dd v ih v il oe v ih v il pgm v ih v il ce v dd
m pd78p4038y 25 figure 6-3. byte program mode flowchart remark g = start address n = program end address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 x = x + 1 0.1 ms program pulse verify address = n ? write end defective verify all bytes v dd = 4.5-5.5 v, v pp = v dd address = address + 1 fail pass fail all pass yes x = 10 ? no yes pass no
m pd78p4038y 26 figure 6-4. byte program mode timing cautions 1. add v dd before v pp , and turn off the v dd after v pp . 2. do not allow v pp to exceed +13.5 v including overshoot. 3. reliability problems may result if the device is inserted or pulled out while +12.5 v is applied at v pp . program program verify data input data output a0-a16 d0-d7 v pp v dd v pp v dd +1.5 v dd v dd v ih v il ce v ih v il pgm v ih v il oe
m pd78p4038y 27 6.3 prom read sequence follow this sequence to read the prom contents to an external data bus (d0 to d7). (1) set the reset pin to low level and add +5 v to the v pp pin. see (2) in chapter 2 with regard to handling of other, unused pins. (2) add +5 v to the v dd and v pp pins. (3) input the data address to be read to pins a0 to a16. (4) set read mode. (5) output the data to pins d0 to d7. figure 6-5 shows the timing of steps (2) to (5) above. figure 6-5. prom read timing address input data output ce (input) a0-a16 oe (input) d0-d7 hi-z hi-z
m pd78p4038y 28 7. erasure characteristics ( m pd78p4038ykk-t only) data written in the m pd78p4038ykk-t program memory can be erased (ffh); therefore users can write other data in the memory. to erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. normally, ultraviolet light with a wavelength of 254 nm is employed. the amount of light required to completely erase the data is as follows: ? intensity of ultraviolet light erasing time: 57.6 w?s/cm 2 min. ? erasing time: about 80 minutes (when using a 12,000 m w/cm 2 ultraviolet lamp. it may, however, take more time due to lamp deterioration, dirt on the erasure window, or the like.) the ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. in addition, if a filter is attached to the ultraviolet lamp, remove the filter before erasure. 8. protective film covering the erasure window ( m pd78p4038ykk-t only) to prevent eprom from being erased inadvertently by light other than that from the lamp used for erasing eprom, or to prevent the internal circuits other than eprom from malfunctioning by light, stick a protective film on the erasure window except when eprom is to be erased. 9. quality the m pd78p4038ykk-t is not intended for use in mass-produced products; they do not have reliability high enough for such purposes. their use should be restricted to functional evaluation in experiment or trial manufacture. 10. screening one-time prom products nec cannot execute a complete test of one-time prom products ( m pd78p4038ygc-3b9, m pd78p4038ygc- 8bt, and m pd78p4038ygk-be9) due to their structure before shipment. it is recommended that you screen (verify) prom products after writing necessary data into them and storing them at 125 c for 24 hours.
m pd78p4038y 29 11. electrical characteristics absolute maximum ratings (t a = 25 c) caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. d/a converter reference input voltage parameter symbol conditions rating unit supply voltage v dd C0.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i1 C0.5 to v dd + 0.5 v v i2 test/v pp pin and C0.5 to +13.5 v p21/intp0/a9 pin in prom programming mode output voltage v o C0.5 to v dd + 0.5 v output low current i ol at one pin 15 ma total of all output pins 100 ma output high current i oh at one pin C10 ma total of all output pins C100 ma a/d converter reference input av ref1 C0.5 to v dd + 0.3 v voltage av ref2 C0.5 to v dd + 0.3 v av ref3 C0.5 to v dd + 0.3 v operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c
m pd78p4038y 30 operating conditions ? operating ambient temperature (t a ) : C40 to +85 c ? rise time and fall time (t r , t f ) (at pins which are not specified) : 0 to 200 m s ? power supply voltage and clock cycle time : see figure 11-1 . figure 11-1. power supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io conditions f = 1 mhz 0 v on pins other than measured pins min. typ. max. 10 10 10 unit pf pf pf 10,000 4,000 1,000 125 100 62.5 10 01234567 guaranteed operating range power supply voltage [v] clock cycle time t cyk [ns]
m pd78p4038y 31 oscillator characteristics (t a = C40 to +85 c, v dd = +4.5 to 5.5 v, v ss = 0 v) caution when using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: ? minimize the wiring. ? never cause the wires to cross other signal lines. ? never cause the wires to run near a line carrying a large varying current. ? cause the grounding point of the capacitor of the oscillator circuit to have the same potential as v ss1 . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator. resonator ceramic resonator or crystal external clock recommended circuit parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) min. 4 4 0 10 max. 32 32 10 125 unit mhz mhz ns ns v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter
m pd78p4038y 32 oscillator characteristics (t a = C40 to +85 c, v dd = +2.7 to 5.5 v, v ss = 0 v) caution when using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: ? minimize the wiring. ? never cause the wires to cross other signal lines. ? never cause the wires to run near a line carrying a large varying current. ? cause the grounding point of the capacitor of the oscillator circuit to have the same potential as v ss1 . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator. resonator ceramic resonator or crystal external clock recommended circuit parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) min. 4 4 0 10 max. 16 16 10 125 unit mhz mhz ns ns v ss1 x1 x2 c2 c1 x1 x2 hcmos inverter
m pd78p4038y 33 dc characteristics (t a = C40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1/2) notes 1. x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, test 2. p40/ad0 to p47/ad7, p50/a8 to p57/a15 3. p60/a16 to p63/a19, p64/rd, p65/wr, p66/wait/hldrq, p67/refrq/hldak 4. p00 to p07 5. p10 to p17 6. p32/sck0/scl, p33/so0/sda parameter input low voltage input high voltage output low voltage output high voltage x1 input low current x1 input high current symbol v il1 v il2 v il3 v ih1 v ih2 v ih3 v ol1 v ol2 v ol3 v oh1 v oh2 i il i ih conditions for pins other than those described in notes 1, 2, 3, 4, and 6 for pins described in notes 1, 2, 3, 4, and 6 v dd = +5.0 v 10% for pins described in notes 2, 3, and 4 for pins other than those described in notes 1 and 6 for pins described in notes 1 and 6 v dd = +5.0 v 10% for pins described in notes 2, 3, and 4 i ol = 2 ma for pins other than those described in note 6 i ol = 3 ma for pins described in note 6 i ol = 6 ma for pins described in note 6 v dd = +5.0 v 10% i ol = 8 ma for pins described in notes 2 and 5 i oh = C2 ma v dd = +5.0 v 10% i oh = C5 ma for pins described in note 4 extc = 0 0 v v i v il2 extc = 0 v ih2 v i v dd min. C0.3 C0.3 C0.3 0.7v dd 0.8v dd 2.2 v dd C 1.0 v dd C 1.4 typ. max. 0.3v dd 0.2v dd +0.8 v dd + 0.3 v dd + 0.3 v dd + 0.3 0.4 0.4 0.6 1.0 C30 +30 unit v v v v v v v v v v v v m a m a
m pd78p4038y 34 dc characteristics (t a = C40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter input leakage current output leakage current v dd supply current pull-up resistor symbol i l| i lo i dd1 i dd2 i dd3 r l conditions 0 v v i v dd for pins other than x1 when extc = 0 0 v v o v dd operation mode f xx = 32 mhz v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v halt mode f xx = 32 mhz v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v idle mode f xx = 32 mhz (extc = 0) v dd = +5.0 v 10% f xx = 16 mhz v dd = +2.7 to 3.3 v v i = 0 v min. 15 typ. 25 12 13 8 max. 10 10 45 25 26 12 12 8 80 unit m a m a ma ma ma ma ma ma k w
m pd78p4038y 35 ac characteristics (t a = C40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter address setup time astb high-level width address hold time (to astb ? ) address hold time (to rd ) delay from address to rd ? address float time (to rd ? ) delay from address to data input delay from astb ? to data input delay from rd ? to data input delay from astb ? to rd ? data hold time (to rd ) delay from rd to address active delay from rd to astb rd low-level width address hold time (to wr ) delay from address to wr ? delay from astb ? to data output delay from wr ? to data output delay from astb ? to wr ? symbol t sast t wsth t hstla t hra t dar t fra t daid t dstid t drid t dstr t hrid t dra t drst t wrl t hwa t daw t dstod t dwod t dstw min. (0.5 + a) t C 15 (0.5 + a) t C 31 (0.5 + a) t C 17 (0.5 + a) t C 40 0.5t C 24 0.5t C 34 0.5t C 14 (1 + a) t C 9 (1 + a) t C 15 0.5t C 9 0 0.5t C 8 0.5t C 12 1.5t C 8 1.5t C 12 0.5t C 17 (1.5 + n) t C 30 (1.5 + n) t C 40 0.5t C 14 (1 + a) t C 5 (1 + a) t C 15 0.5t C 9 max. 0 (2.5 + a + n) t C 37 (2.5 + a + n) t C 52 (2 + n) t C 40 (2 + n) t C 60 (1.5 + n) t C 50 (1.5 + n) t C 70 0.5t + 19 0.5t + 35 0.5t C 11 after program is read after data is read conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10%
m pd78p4038y 36 (1) read/write operation (2/2) note the hold time includes the time during which v oh1 and v ol1 are held under the load conditions of c l = 50 pf and r l = 4.7 k w . remarks t: t cyk (system clock cycle time) n: number of wait states (n 0) (2) bus hold timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns parameter data setup time (to wr ) data hold time (to wr ) note delay from wr to astb wr low-level width symbol t sodw t hwod t dwst t wwl min. (1.5 + n) t C 30 (1.5 + n) t C 40 0.5t C 5 0.5t C 25 0.5t C 12 (1.5 + n) t C 30 (1.5 + n) t C 40 max. conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% unit ns ns ns ns ns ns ns ns parameter delay from hldrq to float delay from hldrq to hldak delay from float to hldak delay from hldrq ? to hldak ? delay from hldak ? to active min. 1t C 20 1t C 30 max. (6 + a + n) t + 50 (7 + a + n) t + 30 (7 + a + n) t + 40 1t + 30 2t + 40 2t + 60 conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% symbol t fhqc t dhqhhah t dcfha t dhqlhal t dhac
m pd78p4038y 37 (3) external wait timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) (4) refresh timing remark t: t cyk (system clock cycle time) parameter delay from address to wait ? input delay from astb ? to wait ? input hold time from astb ? to wait delay from astb ? to wait delay from rd ? to wait ? input hold time from rd ? to wait ? delay from rd ? to wait delay from wait to data input delay from wait to wr delay from wait to rd delay from wr ? to wait ? input hold time from wr ? to wait delay from wr ? to wait unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. (0.5 + n) t + 5 (0.5 + n) t +10 nt + 5 nt + 10 0.5t 0.5t nt + 5 nt + 10 max. (2 + a) t C 40 (2 + a) t C 60 1.5t C 40 1.5t C 60 (1.5 + n) t C 40 (1.5 + n) t C 60 t C 50 t C 70 (1 + n) t C 40 (1 + n) t C 60 0.5t C 5 0.5t C 10 t C 50 t C 75 (1 + n) t C 40 (1 + n) t C 70 conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% symbol t dawt t dstwt t hstwth t dstwth t drwtl t hrwt t drwth t dwtid t dwtw t dwtr t dwwtl t hwwt t dwwth unit ns ns ns ns ns ns ns ns ns parameter random read/write cycle time refrq low-level pulse width delay from astb ? to refrq delay from rd to refrq delay from wr to refrq delay from refrq to astb refrq high-level pulse width max. min. 3t 1.5t C 25 1.5t C 30 0.5t C 9 1.5t C 9 1.5t C 9 0.5t C 15 1.5t C 25 1.5t C 30 symbol t rc t wrfql t dstrfq t drrfq t dwrfq t drfqst t wrfqh conditions v dd = +5.0 v 10% v dd = +5.0 v 10%
m pd78p4038y 38 serial operation (t a = C40 to +85 c, v dd = +2.7 to 5.5 v, av ss = v ss = 0 v) (1) csi remarks 1. the values in this table are those when c l is 100 pf. 2. t : serial clock cycle set by software. the minimum value is 16/f xx . 3. f xx : oscillator frequency (2) i 2 c unit ns m s ns m s ns m s ns ns ns ns parameter serial clock cycle time (sck0) serial clock low-level width (sck0) serial clock high-level width (sck0) si0 setup time (to sck0 ) si0 hold time (to sck0 ) so0 output delay time (to sck0 ? ) min. 10/f xx + 380 t 5/f xx + 150 0.5t C 40 5/f xx + 150 0.5t C 40 40 5/f xx + 40 0 0 max. 5/f xx + 150 5/f xx + 400 conditions input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output cmos push-pull output (3-wire serial i/o mode) open-drain output (2-wire serial i/o mode), r l = 1 k w symbol t cysk0 t wskl0 t wskh0 t sssk0 t hssk0 t dsbsk1 t dsbsk2 parameter scl clock frequency time to hold low scl clock time to hold high scl clock data hold time data setup time rise time of sda or scl signal fall time of sda or scl signal load capacitance of each bus line symbol f scl t low t high t hd ; dat t su ; dat t r t f cb unit khz m s m s ns ns ns ns pf i 2 c bus in standard mode f xx = 4 to 32 mhz min. max. 0 100 4.7 4.0 300 250 1,000 300 400 i 2 c bus in standard mode f xx = 8 to 32 mhz min. max. 0 400 1.3 0.6 300 900 100 20 + 0.1cb 300 20 + 0.1cb 300 400
m pd78p4038y 39 parameter serial clock cycle time (sck1, sck2) serial clock low-level width (sck1, sck2) serial clock high-level width (sck1, sck2) setup time for si1 and si2 (to sck1, sck2 ) hold time for si1 and si2 (to sck1, sck2 ) output delay time for so1 and so2 (to sck1, sck2 ? ) output hold time for so1 and so2 (to sck1, sck2 ) (3) ioe1, ioe2 remarks 1. the values in this table are those when c l is 100 pf. 2. t: serial clock cycle set by software. the minimum value is 16/f xx . (4) uart, uart2 unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 250 500 t 85 210 0.5t C 40 85 210 0.5t C 40 40 40 0 0.5t cysk1 C 40 max. 50 symbol t cysk1 t wskl1 t wskh1 t sssk1 t hssk1 t dsosk t hsosk conditions input v dd = +5.0 v 10% output internal, divided by 16 input v dd = +5.0 v 10% output internal, divided by 16 input v dd = +5.0 v 10% output internal, divided by 16 when data is transferred unit ns ns ns ns ns ns parameter asck clock input cycle time asck clock low-level width asck clock high-level width symbol t cyask t waskl t waskh min. 125 250 52.5 85 52.5 85 max. conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10%
m pd78p4038y 40 clock output operation remarks n: divided frequency ratio set by software in the cpu (n = 1, 2, 4, 8, 16) t: t cyk (system clock cycle time) other operations remarks t cysmp : sampling clock set by software t cycpu : cpu operation clock set by software in the cpu unit ns ns ns ns ns ns ns ns ns parameter clkout cycle time clkout low-level width clkout high-level width clkout rise time clkout fall time min. nt 0.5t cycl C 10 0.5t cycl C 20 0.5t cycl C 10 0.5t cycl C 20 max. 10 20 10 20 conditions v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% v dd = +5.0 v 10% symbol t cycl t cll t clh t clr t clf unit m s m s ns ns ns ns m s m s m s m s parameter nmi low-level width nmi high-level width intp0 low-level width intp0 high-level width low-level width for intp1- intp3 and ci high-level width for intp1- intp3 and ci low-level width for intp4 and intp5 high-level width for intp4 and intp5 reset low-level width reset high-level width symbol t wnil t wnih t wit0l t wit0h t wit1l t wit1h t wit2l t wit2h t wrsl t wrsh min. 10 10 4t cysmp 4t cysmp 4t cycpu 4t cycpu 10 10 10 10 max. conditions
m pd78p4038y 41 a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = av ref1 = +2.7 to 5.5 v, v ss = av ss = 0 v) note quantization error is not included. this parameter is indicated as the ratio to the full-scale value. remark t cyk : system clock cycle time conditions fr = 1 fr = 0 fr = 1 fr = 0 f xx = 32 mhz, cs = 1 stop mode, cs = 0 min. 8 120 180 24 36 C0.3 typ. 1,000 0.5 2.0 1.0 max. 1.0 1.0 0.8 1/2 av ref1 + 0.3 1.5 5.0 20 symbol t conv t samp v ian r an ai ref1 ai dd1 ai dd2 parameter resolution total error note linearity calibration note quantization error conversion time sampling time analog input voltage analog input impedance av ref1 current av dd supply current v dd = av dd = +5.0 v 10% v dd = av dd = +2.7 to 4.5 v t a = -10 to +85 c unit bit % % % lsb t cyk t cyk t cyk t cyk v m w ma ma m a
m pd78p4038y 42 d/a converter characteristics (t a = C40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) parameter resolution total error settling time output resistance analog reference voltage resistance of av ref2 and av ref3 reference power supply input current symbol r o av ref2 av ref3 r airef ai ref2 ai ref3 conditions load conditions: v dd = av dd = av ref2 4 m w , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: v dd = av dd = av ref2 2 m w , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: 2 m w , 30 pf dacs0, 1 = 55 h dacs0, 1 = 55 h min. 8 0.75v dd 0 4 0 C5 typ. 10 8 max. 0.6 0.8 0.8 1.0 10 v dd 0.25v dd 5 0 unit bit % % % % m s k w v v k w ma ma
m pd78p4038y 43 data retention characteristics (t a = C40 to +85 c) note reset, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, and p33/so0/sda pins ac timing test points parameter data retention voltage data retention current v dd rise time v dd fall time v dd hold time (to stop mode setting) stop clear signal input time oscillation settling time input low voltage input high voltage conditions stop mode v dddr = +2.7 to 5.5 v v dddr = +2.5 v crystal ceramic resonator specific pins note min. 2.5 200 200 0 0 30 5 0 0.9v dddr typ. 30 10 max. 5.5 50 40 0.1v dddr v dddr unit v m a m a m s m s ms ms ms ms v v symbol v dddr i dddr t rvd t fvd t hvd t drel t wait v il v ih 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points v dd - 1 v 0.45 v
m pd78p4038y 44 timing waveform (1) read operation (2) write operation astb a8-a19 ad0-ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8-a19 ad0-ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodw t wwl t hwa
m pd78p4038y 45 hold timing external wait signal input timing (1) read operation (2) write operation astb a8-a19 ad0-ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8-a19 ad0-ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal adtb, a8-a19, ad0-ad7, rd, wr
m pd78p4038y 46 refresh timing waveform (1) random read/write cycle (2) when refresh memory is accessed for a read and write at the same time (3) refresh after a read (4) refresh after a write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql
m pd78p4038y 47 serial operation (1) csi (2) i 2 c (3) ioe1, ioe2 (4) uart, uart2 t high t r t hd;dat t su;dat t f t low scl sda asck, asck2 t waskh t waskl t cyask sck si so output data input data t sssk0 t hssk0 t dsbsk1 t wskl0 t wskh0 t cysk0 sck si so output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1
m pd78p4038y 48 clock output timing interrupt input timing reset input timing clkout t clh t cll t cycl t clf t clr nmi intp0 ci, intp1-intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl
m pd78p4038y 49 external clock timing data retention characteristics x1 t wxh t wxl t cyx t xf t xr v dd reset nmi (clearing by falling edge) nmi (clearing by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait
m pd78p4038y 50 parameter high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage output leakage current v ddp supply voltage v pp supply voltage v ddp supply current v pp supply current symbol v ih v il i lip v oh v ol i lo v ddp v pp i dd i pp symbol note 1 v ih v il i li v oh v ol C v cc v pp i dd i pp dc programming characteristics (t a = 25 5 c, v ss = 0 v) min. 2.2 -0.3 2.4 6.25 4.5 12.2 typ. 6.5 5.0 12.5 10 10 5 1.0 max. v ddp + 0.3 0.8 10 0.45 10 6.75 5.5 12.8 40 40 50 100 unit v v m a v v m a v v v v ma ma ma m a conditions 0 v i v ddp note 2 i oh = C400 m a i ol = 2.1 ma 0 v o v ddp , oe = v ih program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode program memory write mode program memory read mode v pp = v ddp notes 1. symbols for the corresponding m pd27c1001a 2. the v ddp represents the v dd pin as viewed in the programming mode.
m pd78p4038y 51 notes 1. these symbols (except t vds ) correspond to those of the corresponding m pd27c1001a. 2. for m pd27c1001a, read t vds as t vcs . ac programming characteristics (t a = 25 5 c, v ss = 0 v) prom write mode (page program mode) parameter address setup time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe oe pulse width in the data latch pgm setup time ce hold time oe hold time symbol note 1 t as t ces t ds t ah t ahl t ahv t dh t df t vps t vds note 2 t pw t oes t oe t lw t pgms t ceh t oeh min. 2 2 2 2 2 0 2 0 2 2 0.095 2 1 2 2 2 typ. 0.1 1 max. 130 0.105 2 unit m s m s m s m s m s m s m s ns m s m s ms m s ns m s m s m s m s conditions
m pd78p4038y 52 notes 1. these symbols (except t vds ) correspond to those of the corresponding m pd27c1001a. 2. for m pd27c1001a, read t vds as t vcs . prom read mode notes 1. these symbols correspond to those of the corresponding m pd27c1001a. 2. t df is the time measured from when either oe or ce reaches v ih , whichever is faster. prom write mode (byte program mode) parameter address setup time ce set time input data setup time address hold time input data hold time output data hold time v pp setup time v ddp setup time initial program pulse width oe set time valid data delay time from oe symbol note 1 t as t ces t ds t ah t dh t df t vps t vds note 2 t pw t oes t oe symbol note 1 t acc t ce t oe t df t oh unit m s m s m s m s m s ns m s m s ms m s ns conditions max. 130 0.105 2 typ. 0.1 1 min. 2 2 2 2 2 0 2 2 0.095 2 typ. 1 1 min. 0 0 ce = oe = v il oe = v il ce = v il ce = v il or oe = v il ce = oe = v il conditions parameter data output time from address delay from ce ? to data output delay from oe ? to data output data hold time to oe or ce note 2 data hold time to address unit ns m s m s ns ns max. 200 2 2 60
m pd78p4038y 53 prom write mode timing (page program mode) page data latch page program program verify data output hi-z hi-z hi-z a2-a16 a0, a1 d0-d7 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm oe v ih v il v ih v il v ih v il t as t ahl t ds t dh t vps data input t pgms t oe t vds t ahv t df t ah t oeh t ces t ceh t pw t oes t lw
m pd78p4038y 54 prom write mode timing (byte program mode) cautions 1. v ddp must be applied before v pp , and must be cut after v pp . 2. v pp including overshoot must not exceed +13.5 v. 3. plugging in or out the board with the v pp pin supplied with 12.5 v may adversely affect its reliability. prom read mode timing notes 1. for reading within t acc , the delay of the oe input from falling edge of ce must be within t acc -t oe . 2. t df is the time measured from when either oe or ce reaches v ih , whichever is faster. program program verify a0-a16 v pp v ddp v pp v ddp + 1.5 v ddp v ddp ce pgm v ih v il v ih v il t ds t pw hi-z hi-z hi-z d0-d7 v ih v il t as t ds t vps t vds t ces t df t ah t dh t oes t oe data input data output oe a0-a16 ce oe hi-z hi-z d0-d7 data output t ce valid address t acc note 1 t oh t oe note 1 t df note 2
m pd78p4038y 55 12. package drawings 80 pin plastic qfp (14x14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8 0.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 a 17.2 0.4 0.677 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.2 0.4 0.677 0.016 f 0.825 0.032 g 0.825 0.032 h 0.30 0.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1 0.1 0.004 0.004 r5 5 5 5 +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6 0.2 0.063 0.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-5 s 3.0 max. 0.119 max. p 2.7 0.1 0.106 +0.005 ?.004
m pd78p4038y 56 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00 0.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00 0.20 0.551 +0.009 ?.008 a 17.20 0.20 0.677 0.008 g 0.825 0.032 h 0.32 0.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60 0.20 0.063 0.008 l 0.80 0.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40 0.10 0.055 0.004 q 0.125 0.075 0.005 0.003 r3 3 +7 ? +7 ? d 17.20 0.20 0.677 0.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
m pd78p4038y 57 80 pin plastic tqfp (fine pitch) (12 12) item millimeters inches i j 0.50 (t.p.) 0.10 0.004 0.020 (t.p.) note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. a 14.00 0.20 0.551 0.008 b 12.00 0.20 0.472 +0.009 ?.008 c 12.00 0.20 0.472 +0.009 ?.008 d 14.00 0.20 0.551 0.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009 0.002 p80gk-50-be9-5 s 1.27 max. 0.050 max. k 1.00 0.20 0.039 +0.009 ?.008 l 0.50 0.20 0.020 +0.008 ?.009 m 0.145 0.006 0.002 n 0.10 0.004 p 1.05 0.041 q 0.10 0.05 0.004 0.002 r5 5 5 5 +0.05 ?.04 +0.055 ?.045 j n l k m detail of lead end 61 60 41 40 21 20 1 80 a b c d s qr g f p hi m
m pd78p4038y 58 z u1 a t b d c u g f w r s q k m i h j x80kw-65a-1 item millimeters inches a b c d f g h i j k q 14.0 0.2 13.6 3.6 max. 0.06 13.6 0.551 0.008 0.072 0.142 max. 0.003 0.024 (t.p.) 0.535 note r s 0.825 0.825 0.65 (t.p.) 0.032 0.032 each lead centerline is located within 0.06 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 0.018 0.535 t r 2.0 r 0.079 0.551 0.008 14.0 0.2 1.84 u 9.0 0.354 u1 2.1 0.083 +0.004 ?.005 w z 0.10 0.004 80 1 0.45 0.10 0.039 +0.007 ?.006 1.0 0.15 c 0.3 c 0.012 0.75 0.15 0.030 +0.006 ?.007 80 pin ceramic wqfn
m pd78p4038y 59 13. recommended soldering conditions the conditions listed below shall be met when soldering the m pd78p4038y. for details of the recommended soldering conditions, refer to our document semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 13-1. soldering conditions for surface-mount devices (1/2) (1) m pd78p4038ygc-3b9: 80-pin plastic qfp (14 14 2.7 mm) caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). (2) m pd78p4038ygc-8bt: 80-pin plastic qfp (14 14 1.4 mm) caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). soldering process soldering conditions symbol infrared ray reflow peak package's surface temperature: 235 c ir35-00-2 reflow time: 30 seconds or less (210 c or more) maximum allowable number of reflow processes: 2 vps peak package's surface temperature: 215 c vp15-00-2 reflow time: 40 seconds or less (200 c or more) maximum allowable number of reflow processes: 2 wave soldering solder temperature: 260 c or less ws60-00-1 flow time: 10 seconds or less number of flow processes: 1 preheating temperature : 120 c max. (measured on the package surface) partial heating method terminal temperature: 300 c or less C heat time: 3 seconds or less (for one side of a device) soldering process soldering conditions symbol infrared ray reflow peak package's surface temperature: 235 c ir35-00-3 reflow time: 30 seconds or less (210 c or more) maximum allowable number of reflow processes: 3 vps peak package's surface temperature: 215 c vp15-00-3 reflow time: 40 seconds or less (200 c or more) maximum allowable number of reflow processes: 3 wave soldering solder temperature: 260 c or less ws60-00-1 flow time: 10 seconds or less number of flow processes: 1 preheating temperature : 120 c max. (measured on the package surface) partial heating method terminal temperature: 300 c or less C heat time: 3 seconds or less (for one side of a device)
m pd78p4038y 60 table 13-1. soldering conditions for surface-mount devices (2/2) (3) m pd78p4038ygk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm) note maximum number of days during which the product can be stored at a temperature of 25 c and a relative humidity of 65% or less after dry-pack package is opened. caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). soldering process infrared ray reflow vps partial heating method symbol ir35-107-2 vp15-107-2 C soldering conditions peak packages surface temperature: 235 c reflow time: 30 seconds or less (210 c or more) maximum allowable number of reflow processes: 2 exposure limit: 7 days note (10 hours of pre-baking is required at 125 c afterward) non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. peak packages surface temperature: 215 c reflow time: 40 seconds or less (200 c or more) maximum allowable number of reflow processes: 2 exposure limit: 7 days note (10 hours of pre-baking is required at 125 c afterward) non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. terminal temperature: 300 c or less heat time: 3 seconds or less (for one side of a device)
m pd78p4038y 61 appendix a development tools the following development tools are available for system development using the m pd78p4038y. see also (5) . (1) language processing software ra78k4 assembler package for all 78k/iv series models cc78k4 c compiler package for all 78k/iv series models df784038 device file for m pd784038y subseries models cc78k4-l c compiler library source file for all 78k/iv series models (2) prom write tools pg-1500 prom programmer pa-78p4026gc programmer adaptor, connects to pg-1500 pa-78p4038gk pa-78p4026kk pg-1500 controller control program for pg-1500 (3) debugging tools ? when using the in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator for all 78k/iv series models ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter when the pc-9800 series computer (other than a notebook) is used as the host machine ie-70000-cd-if pc card and interface cable when a pc-9800 series notebook is used as the host machine ie-70000-pc-if-c interface adapter when the ibm pc/at tm or compatible is used as the host machine ie-784038-ns-em1 note emulation board for evaluating m pd784038y subseries models np-80gc emulation probe for 80-pin plastic qfp (gc-3b9 and gc-8bt types) np-80gk note emulation probe for 80-pin plastic tqfp (gk-be9 type) ev-9200gc-80 socket for mounting on target system board made for 80-pin plastic qfp (gc-3b9 and gc-8bt types) tgk-080sdw adapter for mounting on target system board made for 80-pin plastic tqfp (fine pitch) (gk-be9 type) ev-9900 tool used to remove the m pd78p4038ykk-t from the ev-9200gc-80 id78k4-ns integrated debugger for ie-78k4-ns sm78k4-ns system simulator for all 78k/iv series models df784038 device file for m pd784038y subseries models note under development
m pd78p4038y 62 ? when using the in-circuit emulator ie-784000-r ie-784000-r in-circuit emulator for all 78k/iv series models ie-70000-98-if-b interface adapter when the pc-9800 series computer (other than a notebook) ie-70000-98-if-c is used as the host machine ie-70000-98n-if interface adapter and cable when a pc-9800 series notebook is used as the host machine ie-70000-pc-if-b interface adapter when the ibm pc/at or compatible is used as the host ie-70000-pc-if-c machine ie-78000-r-sv3 interface adapter and cable when the ews is used as the host machine ie-784038-ns-em1 note emulation board for evaluating m pd784038y subseries models ie-784038-r-em1 ie-78400-r-em emulation board for all 78k/iv series models ie-78k4-r-ex2 note conversion board for 80 pins to use the ie-784038-ns-em1 on the ie-784000-r. the board is not needed when the conventional product ie-784038-r-em1 is used. ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 and gc-8bt types) ep-78054gk-r emulation probe for 80-pin plastic tqfp (fine pitch) (gk-be9 type) for all m pd784038y subseries ev-9200gc-80 socket for mounting on target system board made for 80-pin plastic qfp (gc-3b9 and gc-8bt types) tgk-080sdw adapter for mounting on target system board made for 80-pin plastic tqfp (fine pitch) (gk-be9 type) ev-9900 tool used to remove the m pd78p4038ykk-t from the ev-9200gc-80 id78k4 integrated debugger for ie-784000-r sm78k4 system simulator for all 78k/iv series models df784038 device file for m pd784038y subseries models note under development (4) real-time os rx78k/iv real-time os for 78k/iv series models mx78k4 os for 78k/iv series models
m pd78p4038y 63 (5) notes when using development tools ? the id78k-ns, id78k4, and sm78k4 can be used in combination with the df784038. ? the cc78k4 and rx78k/iv can be used in combination with the ra78k4 and df784038. ? the np-80gc is a product from naito densei machida mfg. co., ltd. (044-822-3813). consult the nec sales representative for purchasing. ? the tgk-080sdw is a product from tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic components division (03-3820-7112) osaka electronic components division (06-244-6672) ? the host machines and operating systems corresponding to each software are shown below. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles [windows] sparcstation tm [sunos tm ] software news tm (risc) [news-os tm ] ra78k4 note cc78k4 note pg-1500 controller note C id78k4-ns C id78k4 sm78k4 C rx78k/iv note mx78k4 note note software under ms-dos
m pd78p4038y 64 appendix b conversion socket (ev-9200gc-80) and conversion adapter (tgk-080sdw) (1) conversion socket (ev-9200gc-80) package drawings and recommended pattern to mount the socket connect the m pd78p4038ykk-t (80-pin ceramic wqfn (14 14 mm)) and ep-78230gc-r to the circuit board in combination with the ev-9200gc-80. figure b-1. package drawings of ev-9200gc-80 (reference) (unit: mm) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g0e item millimeters inches a b c d e f g h i j k l m o n p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f based on ev-9200gc-80 (1) package drawing (in mm) f
m pd78p4038y 65 figure b-2. recommended pattern to mount ev-9200gc-80 on a substrate (reference) (unit: mm) a f d e c b g j k l h i 0.026 ? 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 ? 19=12.35 0.05 0.65 0.02 ? 19=12.35 0.05 f f +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f based on ev-9200gc-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution f
m pd78p4038y 66 (2) conversion adapter (tgk-080sdw) package drawings connect the ep-78054gk-r to the circuit board in combination with the tgk-080sdw. figure b-3. package drawings of tgk-080sdw (reference) (unit: mm) item millimeters inches b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.5 0.10 0.020x0.748=0.374 0.004 d 5.3 0.209 h 1.85 0.2 0.073 0.008 i 3.5 0.138 j 2.0 0.079 e 1.3 0.051 f 3.55 g 0.3 0.012 0.140 item millimeters inches b c 0.5x19=9.5 0.020x0.748=0.374 a 18.0 0.709 d h i 1.58 0.062 j 1.2 0.047 e 0.5x19=9.5 0.020x0.748=0.374 f 11.77 0.463 k 7.64 0.301 l 1.2 0.047 m q 1.2 0.047 r 1.58 0.062 s 3.55 0.140 n 1.58 0.062 o 1.2 p 7.64 0.301 0.047 w 6.8 0.268 x 8.24 0.324 y 14.8 0.583 t c 2.0 c 0.079 u 12.31 v 10.17 0.400 0.485 z 1.4 0.2 0.055 0.008 0.5 1.58 0.020 0.062 g 18.0 0.709 k 3.0 0.118 n 1.4 0.2 0.055 0.008 o 1.4 0.2 0.055 0.008 p h=1.8 1.3 h=0.071 0.051 l 0.25 m 14.0 0.551 0.010 q 0~5 0.000~0.197 f f 11.77 0.5 f 0.463 0.020 f tgk-080sdw-g1e t 2.4 0.094 u 2.7 0.106 v 3.9 0.154 r 5.9 s 0.8 0.031 0.232 f f f f f f f f f f tgk-080sdw (tqpack080sd + tqsocket080sdw) package dimension (unit: mm) e f g p r q q q o o o n ijjj lllm b c a t h d k s m2 screw u a v e c d b w x y z m f r u t v g s k j i h l n o p protrusion : 4 places q note : product by tokyo eletech corporation.
m pd78p4038y 67 appendix c related documents documents related to devices document name document no. english japanese m pd784031y data sheet u11504e u11504j m pd784035y, 784036y, 784037y, 784038y data sheet u10741e u10741j m pd78p4038y data sheet this manual u10742j m pd784038, 784038y sub-series user's manual, hardware u11316e u11316j m pd784038y sub-series special function registers C u11090j 78k/iv series user's manual, instruction u10905e u10905j 78k/iv series instruction summary sheet C u10594j 78k/iv series instruction set C u10595j 78k/iv series application note, software basic C u10095j documents related to development tools (user's manual) document name document no. english japanese ra78k4 assembler package operation u11334e u11334j language u11162e u11162j ra78k series structured assembler preprocessor u11743e u11743j cc78k4 series operation u11572e u11572j language u11571e u11571j cc78k series library source file u12322e u12322j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dos tm ) base eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos tm ) base u10540e eeu-5008 ie-78k4-ns to be released u13356j soon ie-784000-r eeu-1534 u12903j ie-784038-ns-em1 planned planned ie-784038-r-em1 u11383e u11383j ep-78230 eeu-1515 eeu-985 ep-78054gk-r eeu-1468 eeu-932 sm78k4 system simulator windows base reference u10093e u10093j sm78k series system simulator external parts user open u10092e u10092j interface specifications id78k4-ns integrated debugger reference u12796e u12796j id78k4 integrated debugger windows base reference u10440e u10440j id78k4 integrated debugger hp-ux, sunos, news-os base reference u11960e u11960j caution the above documents may be revised without notice. use the latest versions when you design application systems.
m pd78p4038y 68 documents related to software to be incorporated into the product (users manual) document name document no. english japanese 78k/iv series real-time os basic u10603e u10603j installation u10604e u10604j debugger C u10364j os for 78k/iv series mx78k4 basic C u11779j other documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor device c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j semiconductor device quality control/reliability handbook C c12769j guide for products related to microcomputer: other companies C u11416j caution the above documents may be revised without notice. use the latest versions when you design application systems.
m pd78p4038y 69 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconduc- tor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd78p4038y 70 caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. iebus and qtop are trademarks of nec corporation. ms-dos and windows are registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.
m pd78p4038y 71 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 j98. 2
m pd78p4038y some related documents may be preliminary versions. note that, however, what documents are preliminary is not indicated in this document. license not needed : m pd78p4038ykk-t the customer must judge the need for license : m pd78p4038ygc-3b9, m pd78p4038ygc- -3b9, m pd78p4038ygc-8bt m pd78p4038ygk-be9, m pd78p4038ygk- -be9 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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